The present invention relates to semiconductor devices and methods for their manufacture. In particular, the present invention relates to semiconductor devices employing dual layer metal deposition for forming a silicide having decreased roughness between a doped silicon region and a metal silicide region.
One of the major goals of integrated circuit design is to produce ever smaller integrated circuits without forfeiting performance. For instance, in designing metal oxide silicon (MOS) transistors, manufacturing smaller components implies the need to design transistors with shorter gates. When the size of a MOS gate is decreased, it is necessary to decrease the size of the source and drain regions in order to reduce leakage current. However, this reduction in size of source and drain regions creates further problems, as electrical connections between the doped silicon of the source and drain regions and metal interconnects have high characteristic resitivity. Higher source/drain (SID) resistivity results in slower operation of the semiconductor device. The gains obtained by producing semiconductor devices with reduced dimensions are offset by the decrease in device speed caused by increased source/drain resistivity.
One approach to addressing the problem of high source/drain resistivity is through self-aligned suicide (salicide) technology. In general, this approach entails layering a metal such as nickel directly over the source and drain regions of a MOS device. An annealing process causes the metal to diffluse into the doped-silicon region of the device, where a metal silicide is formed. In the case of nickel, a nickel silicide (NiSi) is the metal silicide that is formed. This silicide layer segregates over the doped silicon S/D region. Metal suicides have the advantage of having reduced resistivities as compared to doped-silicon alone. Unreacted metal is then stripped from the device, for instance with a 4:1 mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), leaving a metal silicide layer over the source/drain regions. The silicide layer presents a much lower interface resistivity with respect to metal interconnects than does the doped silicon source or drain region. For example, TiSi2 has a resistivity of 15-20 xcexcxcexa9cm, CoSi2 has a resistivity of 17-20 xcexcxcexa9cm, and NiSi has a resistivity of 12-15 xcexcxcexa9cm.
A typical prior art method of manufacturing a semiconductor device using silicide technology may be envisioned with reference to FIGS. 1-4. A typical prior art semiconductor device 10 is depicted in FIG. 1. Semiconductor device 10 is a metal oxide semiconductor (MOS) device comprising a silicon substrate 12, a doped silicon source region 14a, a doped silicon drain region 14b, a gate dielectric 18 and a gate electrode 16. Typically, source region 14a and drain region 14b will be doped with the same dopant material, such as As, P, or B, depending on whether the substrate 12 is crystalline silicon, p-doped silicon or n-doped silicon. Semiconductor device 10 also has a spacer 180 that provides electrical isolation between the source/drain regions 14a, 14b and the gate electrode 16. The spacer 180 is an insulative material, such as silicon nitride (SiN), silicon dioxide (SiO2) or silicon oxynitride (SiON). The spacer 180 is added after implantation and extension of dopant, such a As, to form the source/drain regions 14a, 14b. 
As discussed above, a semiconductor device such as MOS device 10 will tend to exhibit relatively high resistivity at source 14a and drain 14b. A typical prior art method of overcoming this problem is through application of silicide technology. A first step of a prior art process employing silicide technology is depicted in FIG. 2. A metal layer 106, such as nickel (Ni) is applied to the surface of silicon substrate 12, source 14a, drain 14b, gate dielectric 18 and gate electrode 16. The device 10 is then subjected to one or more rapid thermal annealing (RTA) steps. After the RTA step(s), the unreacted metal layer is removed.
FIG. 3 depicts device 10 after the RTA and unreacted metal removal steps. Source 14a is overlaid with a metal silicide layer 104a, while drain 14b is overlaid with a corresponding metal silicide layer 104b. Gate 16 also has a metal silicide layer 116 formed at its top surface. The metal silicide layers 104a, 104b, 116 provide reduced resistivity to connects (not shown) that will be applied to the metal silicide layers 104a, 104b, 116 of device 10 in later fabrication steps.
However, silicide technology is not without its drawbacks. Among these drawbacks is the tendency of certain silicide layers to form a rough interface between the doped portion of the source/drain regions and their corresponding silicide layers. This has been particularly noted with respect to nickel silicides when used in conjunction with As-doped source/drain regions. FIG. 4 depicts a zoom view of part of a typical prior art device 10 employing silicide technology. The device 10 comprises silicon substrate 12, metal gate dielectric 18, gate electrode 16, doped silicon region 14 and silicide layers 104, 116. The surface between doped silicon region 14 and silicide layer 104 is a rough border 106. Such surface roughness results in greater than optimal resistivity and capacitive reactance, both of which negatively impact device speed. It is therefore desirable to form a smoother border between doped silicon regions and overlying metal silicide layers.
There is a need for a semiconductor device having a improved method of making a smooth border between doped source/drain regions and overlying metal silicide layers, and a method of forming such a semiconductor device when the silicide includes nickel, and the dopant is arsenic.
This and other needs are met by embodiments of the present invention, which provide a method of fabricating a semiconductor device having a silicide junction having a smooth border between a doped silicon region and a mixed metal silicide region, the method comprising providing a silicon substrate having a doped silicon region disposed thereon, applying a layer of cobalt metal over at least the doped silicon region, applying a layer of nickel over at least the cobalt layer, subjecting the silicon substrate, doped-silicon region, cobalt layer and nickel layer to rapid thermal annealing, and removing the cobalt and nickel layers to produce a semiconductor device having a silicide junction having a smooth border between a doped silicon region and a silicide region thereof.
The earlier stated needs are also met by embodiments of the present invention, which provide an integrated circuit device having a silicide junction, having a smooth border between a doped silicon region and a silicide region, comprising: a doped silicon region; a silicide region overlying the doped silicon region, the silicide and doped silicon regions forming a silicide junction having a smooth border between the silicide and doped silicon regions; wherein the silicide region comprises silicon, nickel and cobalt atoms.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings.